PI6CL1001 Integrated Clock Buffer with Level Translation

The Diodes PI6CL1001 low-voltage, low-noise, non-inverting, single-output LVCMOS clock buffer with level translation supports 1.0 V to 1.8 V power supplies, features low jitter, and has the capability to bridge the power supply disparity between clock-source and clock-sink devices. The V_{DD_IN} supply voltage defines the input clock level, and the V_{DD_OUT} supply voltage defines the output clock level. The PI6CL1001 is capable of translating clock levels from low to high or from high to low. It has a fail-safe input that prevents oscillation at the output in the absence of an input signal and allows for input signals before V_DD is supplied. It is available in the small-footprint DFN0808 package.